1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a surface voltage-sustaining region for a lateral high power device and an edge termination for a vertical high voltage device.
2. Description of the Related Art
In Ref. [1], the optimum doping density of the surface voltage-sustaining region (N-type in the following) is disclosed, which has an opposite conductivity type to the substrate. The structure of a diode cell with an interdigitated layout shown in FIG. 1A has the afore mentioned voltage-sustaining region, wherein, 1 represents a P−-type substrate region, 2 represents an N+-type contact region, 3 represents a P+-type contact region, 4 represents an N-type region of the voltage-sustaining region from x=0 to x=L, A stands for the anode, and K stands for the cathode. The solid curve in FIG. 1B indicates the required optimum charge density D of the surface impurities for a maximum breakdown voltage under a distance L. In this figure, D0=qNBWpp, where q is the electron charge, NB is the acceptor concentration of the substrate and Wpp is the depletion width of a one-sided abrupt parallel plane junction made by the same substrate doping concentration (e.g. P−-type) under its breakdown voltage, thus D0 stands for the charge density of the depletion layer in the N+-type region. The value of L in FIG. 1B is 2Wpp. Under this condition, the breakdown voltage of the voltage-sustaining region can achieve 95% of the one-sided abrupt parallel plane junction with the same substrate doping concentration. The optimum charge density profile demonstrated by the solid curve can be approximated by three piece-wise zones (dashed lines 5, 6 and 7 in FIG. 1B), where each has a constant surface charge density, to obtain a breakdown voltage just a little lower than the case of the solid curve. Under such the optimum variation lateral doping, the corresponding profiles of the lateral surface electric field Ex and the surface potential V are illustrated in FIG. 1C and FIG. 1D, respectively. In these figures, Ecrit and VBpp stand for the critical electric field and the breakdown voltage of the one-sided abrupt parallel plane junction with the same substrate doping concentration, respectively. FIG. 1E schematically shows a method to implement approximately the three piece-wise zones of constant surface doping densities. In this figure, there is an N-type region 4 with a uniform doping density in the whole surface voltage-sustaining region, where the charge density is larger than the dashed line 5 shown in FIG. 1B. There is a thin P-type region 8 with uniform doping density covering not totally but partly on the N-type region 4. In the minimum covering section (that is, the section including points A and A′), the net charge density obtained by the charges of donors of the N-type region 4 and that of acceptors of the P-type region 8 is equal to the dashed line 5 in FIG. 1B. In the section, where much more part of the N-type region 4 is covered by the P-type region 8, the net charge density equals the dashed line 6 shown in FIG. 1B. In the right section of FIG. 1E, the N-type region 4 is totally covered by the P-type region 8, the net charge density is equivalent to the dashed line 7 in FIG. 1B. Such a method is a method to use the compensation of different types of dopants at different locations.
It should be noted that the more the number of the piece-wise zones are, the closer the breakdown voltage is to that corresponding to the solid curve case shown in FIG. 1B.
However, it may happen that the appropriate dose of the P-type region 8 and/or the appropriate dose of the N-type region 4 do not exist in a certain CMOS or BiCMOS technology. Besides, in modern deep sub-micron technology, the N-type region 4 is very thin and thus the concentration of donors in this region is very high, which accompanies a low mobility. As a result, the specific on-resistance of a lateral n-MOST by using this technique is very high. Furthermore, if the N-type region 4 is covered by the P-type region 8, the thickness of this N-type region 4 becomes much smaller, which increases the specific on-resistance. Besides, as stated in Ref. [2], when the above method shown in FIG. 1E is used, at the boundary of the P-type region 8 (e.g. at the points A and point A′), there is an electric field parallel to semiconductor surface and perpendicular to the edges of P-type strip 8, which causes a slight decrease of the breakdown voltage.
In the prior work (Ref. [3]), the present inventor proposed a thin film of high permittivity placed on the surface of a semiconductor, where electric displacement lines can be guided from one place to another place of semiconductor surface, which needs some electric displacement. However, high permittivity materials normally have ferro-electricity characteristics, which is only suitable for the devices with voltage varying very slowly. Also, the difficulties are increased when it is required that the high permittivity materials should have the same thermal expansion coefficient with the semiconductor.